1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an array substrate for an in-plane switching (IPS) mode LCD device and method of fabricating the same that is capable of having high luminance and a wide viewing angle.
2. Discussion of the Related Art
The liquid crystal molecules for an LCD device have orientation arrangement characteristics resulting from their thin and long shape. An arrangement direction of the liquid crystal molecules can be controlled by applying an electrical field to them. Thus, the LCD device displays images using a variation of transmittance of the liquid crystal molecules by controlling magnitudes of the electric field. The LCD device including a thin film transistor (TFT) as a switching element, referred to as an active matrix LCD (AM-LCD) device, has excellent high resolution characteristics and displaying characteristics for moving images.
A conventional LCD device includes a first substrate, a second substrate and a liquid crystal layer. The first substrate includes a pixel electrode, and the second substrate includes a color filter layer and a common electrode. The first and second substrates face each other, and the liquid crystal layer is interposed therebetween. The conventional LCD device displays images using a vertical electric field between the pixel and common electrodes. The LCD device using the vertical electric field has a high transmittance and a high aperture ratio. However, the LCD device has a narrow viewing angle, low contrast ratio, and other issues.
To resolve the above-mentioned problems, the IPS mode LCD device having a wide viewing angle may be used.
FIG. 1 is a schematic cross-sectional view of an IPS mode LCD device according to the related art. As shown in FIG. 1, the IPS mode LCD device includes first and second substrates 10 and 40 and a liquid crystal layer LC. The first and second substrates 10 and 40 face each other, and the liquid crystal layer LC is interposed therebetween. The first and second substrates 10 and 40 may be referred to as an array substrate and a color filter substrate, respectively.
A pixel region P is defined on the first substrate 10. A thin film transistor (TFT) T, a common electrode 30 and a pixel electrode 32 are formed on the first substrate 10 in the pixel region P. The TFT T includes a gate electrode 14 on the first substrate 10, a gate insulating layer 16 on the gate electrode 14, a semiconductor layer 18 on the gate insulating layer 16, and source and drain electrodes 20 and 22 on the semiconductor layer 18. The gate and source electrodes 14 and 20 extend from the gate and data lines 12 and 24, respectively, and the source and drain electrodes 20 and 22 are separated from each other. The common and pixel electrode 30 and 32 may be formed of a transparent conductive material. The common and pixel electrode 30 and 32 are alternately arranged with and parallel to each other. The pixel electrode 32 is connected to the TFT T. The liquid crystal layer LC is driven by an electric field induced between the common and pixel electrodes 30 and 32.
Although not shown in FIG. 1, gate and data lines are formed on the first substrate 10 to define the pixel region P, and a common line is formed on the first substrate 10 to apply voltage into the common electrode 30.
The second substrate 40 includes a black matrix 42 and a color filter 44. The black matrix 42 corresponds to the gate line (not shown), the data line (not shown) and the TFT T. The color filter 44, which includes sub-color filters 44a and 44b, corresponds to the pixel region P. The color filter 44 includes one of red R, green G and blue (not shown) color.
FIG. 2 is a schematic plane view of an array substrate for an IPS mode LCD device according to the related art.
The gate and data lines 12 and 24 are formed on the first substrate 10 to define the pixel region P, and a common line 15 is parallel to and separated from the gate line 12. The TFT T is formed in the pixel region P to be connected to the gate and data lines 12 and 24. The TFT T includes the gate electrode 14, the gate insulating layer 16 (of FIG. 1), the semiconductor layer 18 and the source and drain electrodes 20 and 22. The gate and source electrodes 14 and 20 extend from the gate and data lines 12 and 24, respectively, and the source and drain electrodes 20 and 22 are separated from each other. Moreover, the common and pixel electrodes 30 and 32 are formed in the pixel region P. The pixel electrode 32 is connected to the TFT T and alternately arranged with the common electrode 30. The common electrode 30 extends from the common line 15 so as to be perpendicular to the common line 15. The common and pixel electrodes 30 and 32 are parallel to each other.
To improve luminance of images and aperture ratio, the pixel and common electrodes 32 and 30 are formed of the transparent conductive material. However, since the effective electric filed, which drives the liquid crystal layer LC (of FIG. 1), is induced not on the pixel and common electrodes 32 and 30 but between the pixel and common electrode 32 and 30, there are problems of deficiency of luminance and aperture ratio.
To resolve these problems in the IPS mode LCD device, an advanced horizontal in-plane switching (AH-IPS) mode LCD device may be used. The pixel electrodes of the AH-IPS mode LCD device has a much narrower distance between them than the IPS mode LCD device, and the common electrode has a plate shape. The pixel electrodes are formed on the common electrode. The AH-IPS mode LCD device has a wide viewing angle in left and right sides and high contrast ratio. Moreover, there is no color shift.
FIG. 3 is a plane view of an array substrate for an AH-IPS mode LCD device according to the related art.
As shown in FIG. 3, the array substrate for the AH-IPS mode LCD device includes the gate and data lines 54 and 72, the TFT T, the common electrode 52 and the plurality of pixel electrodes 78 on a substrate 50. The gate and data lines 54 and 72 cross each other to define the pixel region P on the substrate 50. The TFT T is connected to the gate and data lines 54 and 72. The TFT T includes the gate electrode 56, the gate insulating layer (not shown), the semiconductor layer 62 and the source and drain electrodes 68 and 70. The semiconductor layer 62 includes an active layer (not shown) and an ohmic contact layer (not shown). The gate and source electrodes 56 and 68 extend from the gate and data lines 54 and 72, respectively, and the drain electrode 70 is separated from the source electrode 68.
The common electrode 52 is plate shaped and is formed in an entire surface of the pixel region. The plurality of pixel electrodes 78 is formed on the common electrode 52. The plurality of pixel electrodes 78 are bar shaped. The plurality of pixel electrodes 78 extend from first and second connection lines 78a and 78b. The plurality of pixel electrodes 78 are connected to one another by the first and second connection lines 78a and 78b. The plurality of pixel electrodes 78 are separated from one another in a center region of the pixel region P. The first connection line 78a is connected to the drain electrode 70, and the second connection line 78b may overlap the gate line 54.
The liquid crystal layer (not shown) is driven by the electric field between the common and pixel electrode 52 and 78. Since the distance between the common and pixel electrodes 52 and 78 is much close than the conventional IPS mode LCD device, the electric field effectively drives liquid crystal molecules of the liquid crystal layer (not shown) on the pixel electrode 78 such that the AH-IPS mode LCD device has higher luminance than the conventional IPS-mode LCD device.
FIGS. 4A and 4B are cross-sectional view taken along the lines IVa-IVa and IVb-IVb of FIG. 3.
As shown in FIG. 4A, the TFT T is formed in pixel region P on the substrate 50. The TFT T includes the gate electrode 56 on the substrate 50, the gate insulating layer 58 on the gate electrode 56, the semiconductor layer 62, which includes the active layer 62a and the ohmic contact layer 62b, on the gate insulating layer 58, the source and drain electrodes 68 and 70 on the semiconductor layer 62.
The common electrode 52 is formed of the transparent conductive material on the substrate 50. An insulating layer 53 is interposed between the common electrode 52 and the gate electrode 56. The first connection line 78a is formed over the TFT T with the passivation layer 74 therebetween. The first connection line 78a is connected to the drain electrode 68 through a drain contact hole 76 of the passivation layer 74.
As shown in FIG. 4B, the plurality of bar shaped pixel electrodes 78 correspond to the common electrode 52. The plurality of pixel electrodes 78 extend from the first connection line 78a (of FIG. 4A) to be connected to one another. The data line 72 is formed on the gate insulating layer 58 and at both sides of the pixel region P.
The AH-IPS mode LCD device has the wide viewing angle and high contrast ratio. However, since the pixel electrodes 78 overlap the common electrode 52, there are a storage capacities generated between the pixel and common electrodes 78 and 52. The storage capacities between the pixel and common electrodes 78 and 52 in the AH-IPS mode LCD device may be five times as much as the storage capacity in the conventional IPS-mode LCD device shown in FIGS. 1 and 2. It requires that the TFT T in the AH-IPS mode LCD device has a greater size than the conventional IPS-mode LCD device shown in FIGS. 1 and 2 such that aperture ratio in the AH-IPS mode LCD device is reduced. Moreover, since the pixel electrodes are arranged to be parallel to the data line 72 (of FIG. 3), the viewing angle in upper and lower sides and a diagonal direction is deteriorated.